High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.4
DC Specifications
Table 15.3 I/O Buffer Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
IS Type Input Buffer
Low Input Level
V
-0.3
V
V
ILI
IHI
ILT
IHT
High Input Level
V
V
3.6
1.35
1.8
Negative-Going Threshold
Positive-Going Threshold
SchmittTrigger Hysteresis
1.01
1.39
345
1.18
1.6
V
Schmitt trigger
Schmitt trigger
V
V
V
420
485
mV
HYS
(V
- V
)
IHT
ILT
Input Leakage
I
-10
10
3
uA
pF
Note 15.5
IN
Input Capacitance
O8 Type Buffers
C
IN
Low Output Level
V
0.4
V
V
I
= 8mA
OL
OL
VDD33IO - 0.4
High Output Level
OD8 Type Buffer
V
I
= -8mA
OH
OH
Low Output Level
O12 Type Buffer
V
V
0.4
0.4
V
I
= 8mA
OL
OL
Low Output Level
V
V
I
= 12mA
= -12mA
OL
OL
VDD33IO - 0.4
High Output Level
OD12 Type Buffer
V
I
OH
OH
Low Output Level
V
0.4
V
I
= 12mA
OL
OL
ICLK Type Buffer (XI Input)
Note 15.6
Low Input Level
High Input Level
V
-0.3
1.4
0.5
3.6
V
V
ILI
V
IHI
Note 15.5 This specification applies to all IS type inputs and tri-stated bi-directional pins. Internal pull-
down and pull-up resistors add +/- 50uA per-pin (typical).
Note 15.6 XI can optionally be driven from a 25MHz single-ended clock oscillator.
Table 15.4 100BASE-TX Transceiver Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Peak Differential Output Voltage High
Peak Differential Output Voltage Low
Signal Amplitude Symmetry
Signal Rise and Fall Time
V
950
-950
98
-
-
1050
-1050
102
5.0
mVpk
mVpk
%
Note 15.7
Note 15.7
Note 15.7
Note 15.7
Note 15.7
Note 15.8
PPH
V
PPL
V
-
SS
RF
T
3.0
-
-
nS
Rise and Fall Symmetry
T
-
0.5
nS
RFS
Duty Cycle Distortion
D
35
50
65
%
CD
SMSC LAN9312
443
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
