High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
PIN / DEFAULT
VALUE
STRAP NAME
DESCRIPTION
speed_strap_1
Port 1 Speed Select Strap: Configures the default value
for the Speed Select LSB (PHY_SPEED_SEL_LSB) bit in
the PHY_BASIC_CTRL_1 register (See Section 14.4.2.1).
When configured low, 10 Mbps is selected. When
configured high, 100 Mbps is selected.
1b
This strap also affects the default value of the following bits:
PHY_SPEED_SEL_LSB bit of the Port x PHY Basic
Control Register (PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x)
MODE[2:0] bits of the Port x PHY Special Modes Register
(PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
duplex_strap_1
Port 1 Duplex Select Strap: Configures the default value
for the Duplex Mode (PHY_DUPLEX) bit in the
PHY_BASIC_CTRL_1 register (See Section 14.4.2.1).
When configured low, half-duplex is selected. When
configured high, full-duplex is selected.
1b
This strap also affects the default value of the following bits:
PHY_DUPLEX bit of the Port x PHY Basic Control
Register (PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex (bit 6) of the Port x PHY Auto-
Negotiation Advertisement Register (PHY_AN_ADV_x)
MODE[2:0] bits of the Port x PHY Special Modes Register
(PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
BP_EN_strap_1
FD_FC_strap_1
Port 1 Backpressure Enable Strap: Configures the
default value for the Port 1 Backpressure Enable
(BP_EN_1) bit of the Port 1 Manual Flow Control Register
(MANUAL_FC_1). When configured low, backpressure is
disabled. When configured high, backpressure is enabled.
1b
1b
Port 1 Full-Duplex Flow Control Enable Strap:
Configures the default value of the Port 1 Full-Duplex
Transmit Flow Control Enable (TX_FC_1) and Port 1 Full-
Duplex Receive Flow Control Enable (RX_FC_1) bits in the
Port 1 Manual Flow Control Register (MANUAL_FC_1),
which are used when manual full-duplex control is selected.
When configured low, full-duplex Pause packet detection
and generation are disabled. When configured high, full-
duplex Pause packet detection and generation are enabled.
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA4S2HEET