High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
DESCRIPTION
PIN / DEFAULT
VALUE
STRAP NAME
manual_FC_strap_2
Port 2 Manual Flow Control Enable Strap: Configures the
default value of the Port 2 Full-Duplex Manual Flow Control
Select (MANUAL_FC_2) bit in the Port 2 Manual Flow
Control Register (MANUAL_FC_2). When configured low,
flow control is determined by auto-negotiation (if enabled),
and symmetric PAUSE is advertised (bit 10 of the Port x
PHY Auto-Negotiation Advertisement Register
0b
(PHY_AN_ADV_x) is set).
When configured high, flow control is determined by the
Port 2 Full-Duplex Transmit Flow Control Enable
(TX_FC_2) and Port 2 Full-Duplex Receive Flow Control
Enable (RX_FC_2) bits, and symmetric PAUSE is not
advertised (bit 10 of the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x) is cleared).
BP_EN_strap_mii
FD_FC_strap_mii
Port 0(Host MAC) Backpressure Enable Strap:
Configures the default value for the Port 0 Backpressure
Enable (BP_EN_MII) bit of the Port 0(Host MAC) Manual
Flow Control Register (MANUAL_FC_MII). When
configured low, backpressure is disabled. When configured
high, backpressure is enabled.
1b
1b
Port 0(Host MAC) Full-Duplex Flow Control Enable
Strap: Configures the default of the TX_FC_MII and
RX_FC_MII bits in the Port 0(Host MAC) Manual Flow
Control Register (MANUAL_FC_MII) which are used when
manual full-duplex flow control is selected. When
configured low, flow control is disabled on RX/TX. When
configured high, flow control is enabled on RX/TX.
manual_FC_strap_mii
Port 0(Host MAC) Manual Flow Control Enable Strap:
Configures the default value of the MANUAL_FC_MII bit in
the Port 0(Host MAC) Manual Flow Control Register
(MANUAL_FC_MII). When configured low, flow control is
determined by Virtual Auto-Negotiation (if enabled). When
configured high, flow control is determined by TX_FC_MII
and RX_FC_MII bits in the Port 0(Host MAC) Manual Flow
Control Register (MANUAL_FC_MII).
0b
SQE_test_disable_strap_mii
SQE Heartbeat Disable Strap: Configures the Signal
Quality Error (Heartbeat) test function by controlling the
default value of the SQEOFF (bit 0) of the Virtual PHY
Special Control/Status Register
0b
(VPHY_SPECIAL_CONTROL_STATUS). When configured
low, SQEOFF defaults to 0 and SQE test is enabled. When
configured high, SQEOFF defaults to 1 and SQE test is
disabled.
4.2.4.2
Hard-Straps
Hard-straps are latched upon Power-On Reset (POR) or pin reset (nRST) only. Unlike soft-straps,
hard-straps always have an associated pin and cannot be overridden by the EEPROM Loader. These
straps are used as either direct configuration values or as register defaults. Table 4.3 provides a list of
all hard-straps and their associated pin. These straps, along with their pin assignments are also fully
defined in Chapter 3, "Pin Description and Configuration," on page 26.
SMSC LAN9312
Revision 1.2 (04-08-08)
DATA4S5HEET
SMSC [ SMSC CORPORATION ]
