High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Note: When using the Reset bit to reset the Port 1 PHY, register bits designated as NASR are not
reset.
Refer to Section 7.2.10, "PHY Resets," on page 95 for additional information on Port 1 PHY resets.
4.2.3.3
Virtual PHY Reset
A Virtual PHY reset is performed by setting the VPHY_RST bit of the Reset Control Register
(RESET_CTL), VPHY_RST bit in the Power Management Control Register (PMT_CTRL), or Reset in
the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). No other modules of the LAN9312 are
affected by this reset.
Virtual PHY reset completion can be determined by polling the VPHY_RST bit in the Reset Control
Register (RESET_CTL), the VPHY_RST bit in the Power Management Control Register (PMT_CTRL),
or the Reset bit in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) until it clears. Under
normal conditions, the VPHY_RST and Reset bit will clear approximately 1uS after the Virtual PHY
reset occurrence.
Refer to Section 7.3.2, "Virtual PHY Resets," on page 98 for additional information on Virtual PHY
resets.
4.2.4
Configuration Straps
Configuration straps allow various features of the LAN9312 to be automatically configured to user
defined values. Configuration straps can be organized into two main categories: hard-straps and soft-
straps. Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST).
The primary difference between these strap types is that soft-strap default values can be overridden
by the EEPROM Loader, while hard-straps cannot.
Configuration straps which have a corresponding external pin include internal resistors in order to
prevent the signal from floating when unconnected. If a particular configuration strap is connected to
a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to
ensure that it reaches the required voltage level prior to latching. The internal resistor can also be
overridden by the addition of an external resistor.
Note: The system designer must guarantee that configuration strap pins meet the timing
requirements specified in Section 15.5.2, "Reset and Configuration Strap Timing," on page 445.
If configuration strap pins are not at the correct voltage level prior to being latched, the
LAN9312 may capture incorrect strap values.
4.2.4.1
Soft-Straps
Soft-strap values are latched on the release of POR or nRST and are overridden by values from the
EEPROM Loader (when an EEPROM is present). These straps are used as direct configuration values
or as defaults for CPU registers. Some, but not all, soft-straps have an associated pin. Those that do
not have an associated pin, have a tie off default value. All soft-strap values can be overridden by the
EEPROM Loader. Table 4.2 provides a list of all soft-straps and their associated pin or default value.
Straps which have an associated pin are also fully defined in Chapter 3, "Pin Description and
Configuration," on page 26. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for information
on the operation of the EEPROM Loader and the loading of strap values.
Upon setting the DIGITAL_RST bit in the Reset Control Register (RESET_CTL) or upon issuing a
RELOAD command via the EEPROM Command Register (E2P_CMD), these straps return to their
original latched (non-overridden) values if an EEPROM is no longer attached or has been erased. The
associated pins are not re-sampled. (i.e. The value latched on the pin during the last POR or nRST
will be used, not the value on the pin during the digital reset or RELOAD command issuance). If it is
desired to re-latch the current configuration strap pin values, a POR or nRST must be issued.
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA4S0HEET
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