High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
A POR reset typically takes approximately 23mS, plus additional time (91uS for I2C, 28uS for
Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load
(64KB for I2C, 2KB for Microwire) will complete in approximately 6.0 seconds for I2C EEPROM, and
80mS for Microwire EEPROM.
4.2.1.2
nRST Pin Reset
Driving the nRST input pin low initiates a chip-level reset. This event resets all circuitry within the
device. Use of this reset input is optional, but when used, it must be driven for the period of time
specified in Section 15.5.2, "Reset and Configuration Strap Timing," on page 445. Configuration straps
are latched, and the EEPROM Loader is run as a result of this reset.
A nRST pin reset typically takes approximately 760uS, plus additional time (91uS for I2C, 28uS for
Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load
(64KB for I2C, 2KB for Microwire) will complete in approximately 6.0 seconds for I2C EEPROM, and
58mS for Microwire EEPROM.
Note: The nRST pin is pulled-high internally. If unused, this signal can be left unconnected. Do not
rely on internal pull-up resistors to drive signals external to the device.
Please refer to Section Table 3.7, "Miscellaneous Pins," on page 33 for a description of the nRST pin.
4.2.2
Multi-Module Resets
Multi-module resets activate multiple internal resets, but do not reset the entire chip. Configuration
straps are not latched upon multi-module resets. A multi-module reset is initiated by assertion of the
following:
Digital Reset (DIGITAL_RST)
Soft Reset (SRST)
Chip-level reset completion/configuration can be determined by polling the READY bit of the Hardware
Configuration Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set.
When set, the READY bit indicates that the reset has completed and the device is ready to be
accessed.
With the exception of the Hardware Configuration Register (HW_CFG), Power Management Control
Register (PMT_CTRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register
(RESET_CTL), read access to any internal resources is forbidden while the READY bit is cleared.
Writes to any address are invalid until the READY bit is set.
Note: The digital reset and soft reset do not reset register bits designated as NASR.
Note: The LAN9312 must be read at least once after a multi-module reset to ensure that write
operations function properly.
4.2.2.1
Digital Reset (DIGITAL_RST)
A digital reset is performed by setting the DIGITAL_RST bit of the Reset Control Register
(RESET_CTL). A digital reset will reset all LAN9312 sub-modules except the Ethernet PHYs (Port 1
PHY, Port 2 PHY, and Virtual PHY). The EEPROM Loader will automatically run following this reset.
Configuration straps are not latched as a result of a digital reset.
A digital reset typically takes approximately 760uS, plus additional time (91uS for I2C, 28uS for
Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load
(64KB for I2C, 2KB for Microwire) will complete in approximately 6.0 seconds for I2C EEPROM, and
58mS for Microwire EEPROM.
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA3S8HEET
SMSC [ SMSC CORPORATION ]
