Notes: 1. HARD RESET: RESET_DRV pin asserted
2. SOFT RESET: Bit 0 of Configuration Control register set to one
3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing
Diagram)
Table 75 - Configuration Registers
HARD RESET
/ Vcc POR
SOFT
RESET
INDEX
TYPE
VTR POR
CONFIGURATION REGISTER
GLOBAL CONFIGURATION REGISTERS
0x02
0x03
0x07
0x20
0x21
0x22
0x23
0x24
0x26
W
0x00
0x00
n/a
Config Control
R/W
R/W
R
0x03
0x00
0x03
0x01
0x00
0x00
0x04
Index Address
0x00
0x03
0x01
0x00
n/a
Logical Device Number
Device ID - hard wired
Device Rev - hard wired
Power Control
R
R/W
R/W
R/W
R/W
Power Mgmt
n/a
OSC
Sysopt=0:
0xF0
n/a
Configuration Port Address Byte 0
Sysopt=1:
0x70
Sysopt=0:
0x03
0x27
R/W
n/a
Configuration Port Address Byte 1
Sysopt=1:
0x03
0x28
0x2D
0x2E
0x2F
R/W
R/W
R/W
R/W
0x00
0x00
n/a
Clock Mask Register
TEST 1
n/a
n/a
n/a
TEST 2
0x00
n/a
TEST 3
LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD)
0x30
R/W
R/W
0x00
0x00
Activate
0x60,
0x61
0x03,
0xF0
0x03,
0xF0
Primary Base I/O Address
0x70
0x74
0xF0
R/W
R/W
R/W
0x06
0x02
0x0E
0x06
0x02
n/a
Primary Interrupt Select
DMA Channel Select
FDD Mode Register
171
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