GateA20 Logic
64&nAEN
KRST_GA20
Bit 1
A
nIOW
nIOW
DD1
nIOW
DFF
DFE
8042
Address
A
KRST_GA20
Bit 0
CPURST
To KRESET Gen
nAEN&60
GPI/O Polarity
Config
A20GATE
nIOW
GA20
MUX
DD1
GateA20
After D1
D[1]
nIOW
KRST_GA20
Bit 1
nAEN&64
nIOW
D
nAEN&60
Trailing Edge Delay
KRST_GA20
Bit 2
ALT_A20
P92
Bit 1
Delay
VCC
Note: When Port 92 is disabled,
writes are ignored and reads
return undefined values.
A
nIOW
24MHz
Note: Use 64 and 60 or the alternate addresses
for command and data ports.
FIGURE 7 - GATEA20 GENERATION LOGIC
The timing for a D1 command write followed by
a data write is shown on the following page.
This is the GATEA20 turn-on sequence
shown in the table “GATE20 Command/Data
Sequence Examples” on page 143.
142
SMSC [ SMSC CORPORATION ]
