Table 63 - GATEA20 Command/Data Sequence Examples
SA2
R/W
D[0:7]
IBF FLAG
GATEA20
COMMENTS
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
D1
D[1]=1
FF
D1
D[1]=0
FF
D1
D1
D[1]=1
FF
D1
D1
D[1]=0
FF
D1
XX**
FF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Q
1
Q
Q
0
Q
Q
Q
1
Q
Q
Q
0
GATEA20 Turn-on Sequence
GATEA20 Turn-off Sequence
GATEA20 Turn-on
Sequence(*)
GATEA20 Turn-off
Sequence(*)
Q
Q
Q
Q
Invalid Sequence
Notes:
"Q" indicates the bit remains set at the previous state.
*Not a standard sequence.
**XX = Anything except D1.
If multiple data bytes, set IBF and wait at state 0. Let the software know something unusual
happened.
For data bytes SA2=0, only D[1] is used; all other bits are don't care.
The polarity control bit for GPI/O controls the polarity of GATEA20.
Table 64 details the possible KRESET sequences and the chip responses.
Table 64 - KRESET Command/Data Sequence Examples
SA2
R/W
D[0:7]
IBF FLAG
COMMENTS
1
W
FE
0
Pulse KRESET
When an FE command is received, pulse
KRESET. KRESET is pulsed low for
The polarity control bit for GPI/O controls the
polarity of KRESET.
a
minimum of 6µs pulse width after a minimum of
a 14µs delay.
145
SMSC [ SMSC CORPORATION ]
