Table 60 - Port 92 Register
BIT
FUNCTION
0
Alternate System Reset. This read/write bit provides an alternate system reset
function. This function provides an alternate means to reset the system CPU to
effect a mode switch from Protected Virtual Address Mode to the Real Address
Mode. This provides a faster means of reset than is provided by the Keyboard
controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will
cause the nALT_RST signal to pulse acitive (low) for a minimum of 1 µs after a
delay of 500 ns. Before another nALT_RST pulse can be generated, this bit
must be written back to a 0.
Table 61 - nGATEA20
8042
ALT_A20
System
P21
0
0
1
1
nA20M
0
1
0
1
0
1
1
1
Bit 0 of Port 92, which generates the nALT_RST
signal, is used to reset the CPU under program
The diagram on the following page illustrates
the generation of the nALT_RST function. If
software control is selected, i.e., bit 0 of
KRST_GA20 is set to 0, the reset pulse is
generated by the 8042 upon writing an FE
command to register 64. If hardware speed-up
is selected, i.e., bit 0 of KRST_GA20 is set to 1,
the reset pulse is generated in hardware upon
writing an FE command to register 64.
control.
This signal is ANDed together
externally with the reset signal (nKBDRST) from
the keyboard controller to provide a software
means of resetting the CPU. This provides a
faster means of reset than is provided by the
keyboard controller. Writing a 1 to bit 0 in the
Port 92 Register causes this signal to pulse low
for a minimum of 6µs, after a delay of a
minimum of 14µs. Before another nALT_RST
pulse can be generated, bit 0 must be set to 0
either by a system reset of a write to Port 92.
Upon reset, this signal is driven inactive high (bit
0 in the Port 92 Register is set to 0).
In addition, if Port 92 is enabled, i.e., bit 2 of
KRST_GA20 is set to 1, then a pulse is also
generated by writing a 1 to bit 0 of the Port 92
Register and this pulse is ANDed with the pulse
generated above. This pulse is output on pin
KRESET and its polarity is controlled by the
GPI/O polarity configuration.
140
SMSC [ SMSC CORPORATION ]
