4. Update Ended Interrupt Flag (UF) bit is
cleared to 0.
REAL TIME CLOCK
5. Interrupt Request Status Flag (IRQF) bit is
cleared to 0.
6. Periodic Interrupt Flag (PIF) is cleared to 0.
7. The RTC and CMOS registers are not
accessable.
The Real Time Clock is a complete time of day
clock with two alarms, calendar (up to the year
9999), a programmable periodic interrupt, and a
programmable square wave generator.
8. Alarm Interrupt Flag (AF) is cleared to 0.
9. nIRQ pin is in high impedance state.
Features
·
·
Counts seconds, minutes, and hours of the
day.
Counts days of the week, date, month, year
and century.
When RESET_DRV is active and the battery
voltage is below 1 volt nominal, the following
occurs:
·
·
·
Time of Day Alarm
1. Registers 00-0D are initialized to 00h.
2. Access to all registers from the host or
FDC37C93xFR CPU (8042) are blocked.
Time Of Century Wake-Up Alarm
Binary or BCD representation of time,
calendar and alarms.
·
·
Three interrupts
software maskable. (No daylight savings
time!)
-
each is separately
RTC Interrupt
The interrupt generated by the RTC is an active
high output. The RTC interrupt output remains
high as long as the status bit causing the
interrupt is present and the corresponding
256 Bytes of CMOS RAM.
Port Definition and Description
interrupt-enable bit is set.
RESET_DRV or reading register C clears the
RTC interrupt.
Activating
OSC
Crystal Oscillator input. Maximum clock
frequency is 32.768 KHz.
The RTC Interrupt is brought out by
programming the RTC Primary Interrupt Select
to a non-zero value. If IRQ 8 is selected then
RTC Reset
the polarity of this IRQ
programmable through a bit in the OSC Global
Configuration Register.
8
output is
The clock, calendar, or RAM functions are not
affected by the system reset (RESET_DRV
active). When the RESET_DRV pin is active
(i.e., system reset) and the battery voltage is
above 1 volt nominal, the following occurs:
Internal Registers
Table 65A shows the address map of the RTC,
ten bytes of time, calendar, and alarm 1 data,
four control and status bytes and 114 bytes of
"CMOS" registers.
1. Periodic Interrupt Enable (PIE) is cleared to
0.
2. Alarm Interrupt Enable (AIE) bit is cleared
to 0.
3. Update Ended Interrupt Enable (UIE) bit is
cleared to 0.
146
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