Host I/F Status Register
The Status register is 8 bits wide. Table 58
shows the contents of the Status register.
Table 58 - Status Register
D7
D6
D5
D4
D3
D2
D1
D0
UD
UD
UD
UD
C/D
UD
IBF
OBF
Status Register
OBF
(Output Buffer Full) - This flag is set to
“1” whenever the FDC37C93xFR CPU
writes to the output data register
(DBB). When the host system reads
the output data register, this bit is
automatically reset.
This register is cleared on a reset. This register
is read-only for the Host and read/write by the
FDC37C93xFR CPU.
UD
Writeable by FDC37C93xFR CPU.
These bits are user-definable.
EXTERNAL CLOCK SIGNAL
The FDC37C93xFR’s X1K clock source is a 12
MHz clock generated from a 14.318 MHz clock.
The reset pulse must last for at least 24 16 MHz
clock periods. The pulse-width requirement
applies to both internally-and externally-
generated reset signals. In powerdown mode,
the external clock signal on X1K is not loaded by
the chip.
C/D
(Command Data)-This bit specifies
whether the input data register contains
data or a command (0 = data, 1 =
command).
During
a
host
data/command write operation, this bit
is set to "1" if SA2 = 1 or reset to "0" if
SA2 = 0.
IBF
(Input Buffer Full) - This flag is set to
“1” whenever the host system writes
data into the input data register. Setting
this flag activates the FDC37C93xFR’s
CPU's nIBF (MIRQ) interrupt if
The FDC37C93xFR’s X1C clock source must be
from a crystal connected across X1C and X2C.
Due to the low current internal oscillator circuit,
this X1C can not be driven by an external clock
signal.
enabled.
When the FDC37C93xFR
CPU reads the input data register
(DBB), this bit is automatically reset
and the interrupt is cleared. There is
no output pin associated with this
internal signal.
DEFAULT RESET CONDITIONS
The FDC37C93xFR has one source of reset: an
external reset via the RESET pin. Refer to
Table 59 for the effect of each type of reset on
the internal registers.
138
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