address line A20 to emulate 8086 addressing.
FAST GATEA20 AND KEYBOARD RESET
GateA20 / KRESET Hardware Speed-Up
GATEA20 and KRESET is configured via a byte
at F0 in the keyboard configuration space,
Logical Device 7. The byte is defined in table 62
below. (Engineering Note: This represents an
addition to the FDC37C93x configuration
space).
The FDC37C93xFR contains on-chip logic
support for the GATEA20 and KRESET
hardware speed-up feature. GATEA20 from the
chip is part of the control required to mask
Table 62 - KRESET Hardware Speed-Up
REG INDEX DESCRIPTION
0xF0 Bits[7:3] Reserved
NAME
KRST_GA20
STATE
C
Bit[2] Port 92 Select
= 0 Port 92 Disabled
= 1 Port 92 Enabled
Bit[1] GATEA20 Select
= 0 8042 Software Control
= 1 Hardware Speed-up
Bit[0] KRESET Select
= 0 8042 Software Control
= 1 Hardware Speed-up
When the chip receives a "D1" command
followed by data (via the host interface), the on-
chip hardware copies the value of data bit 1 in
the received data field to the GATEA20 host
latch. It also copies the value of D[0] to
KRESET latch. At no time during this host-
interface transaction will PCOBF or the IBF flag
(bit 1) in the Status register be activated; i.e.,
this host control of GATEA20 is transparent to
firmware, with no consequent degradation of
overall system performance. Table 63 details
the possible GATEA20 sequences and the chip
responses.
On VCC1 POR, GATEA20 and KRESET pins
will float.
GATEA20 comes from either the software
control or hardware speed-up and they are
mutually exclusive.
If Port 92 is enabled,
GATEA20 from one of these two are merged
along with Port 92. See Port 92 Section.
KRESET comes from either the software control
or hardware speed-up and they are mutually
exclusive. If Port 92 is enabled, KRESET from
one of these two are merged along with Port 92.
See Port 92 Section.
144
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