RTC Data Register
CPU-to-Host Communication
A read of this register will read the contents of
the selected CMOS register. A write to this
register will write to the selected CMOS register.
The FDC37C93xFR CPU can write to the Output
Data register via register DBB. A write to
this register automatically sets Bit 0 (OBF) in
the Status register. See Table 57.
Table 57 - Host Interface Flags
8042 INSTRUCTION
FLAG
OUT DBB
Set OBF, and, if enabled, the KIRQ output signal goes high
If "EN FLAGS” has not been executed; KIRQ
can be controlled by writing to P24. Writing a
Host-to-CPU Communication
“0” to P24 forces KIRQ low; a high forces KIRQ
high.
The host system can send both commands and
data to the Input Data register. The CPU
differentiates between commands and data by
reading the value of Bit 3 of the Status register.
When bit 3 is "1", the CPU interprets the register
contents as a command. When bit 3 is "0", the
CPU interprets the register contents as data.
During a host write operation, bit 3 is set to "1" if
SA2 = 1 or reset to "0" if SA2 = 0.
MIRQ
If "EN FLAGS" has been executed and P25 is
set to a “1”, IBF is inverted and gated onto
MIRQ. The MIRQ signal can be connected to
system
interrupt
to
signify
that
the
FDC37C93xFR’s CPU has read the DBB
register.
KIRQ
If "EN FLAGS" has been executed and P24 is
set to a one: the OBF flag is gated onto KIRQ.
The KIRQ signal can be connected to system
interrupt to signify that the FDC37C93xFR’s
CPU has written to the output data register via
"OUT DBB, A". If P24 is set to a “0”, KIRQ is
forced low. On power-up, after a valid RST
pulse has been delivered to the device, KIRQ is
reset to 0. KIRQ will normally reflects the status
of writes "DBB". (KIRQ is normally selected as
IRQ1 for keyboard support.)
If "EN FLAGS” has not been executed, MIRQ is
controlled by P25. Writing a “0” to P25 forces
MIRQ low; a high forces MIRQ high. (MIRQ is
normally selected as IRQ12 for mouse support.)
Gate A20
A general purpose P21 can be routed out to the
general purpose pin GP25 for use as
a
software-controlled Gate A20 or user-defined
output.
136
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