interrupt and the IBF interrupt is enabled, then
program execution resumes with a CALL to the
interrupt routine, otherwise the next instruction
is executed. If it is exited using RESET, then a
normal reset sequence is initiated and program
execution starts from program memory location
0.
EXTERNAL
INTERFACE
KEYBOARD
AND
MOUSE
Industry-standard PCAT-compatible keyboards
employ a two-wire, bidirectional TTL interface
for data transmission. Several sources also
supply PS/2 mouse products that employ the
same type of interface. To facilitate system
expansion, the FDC37C93xFR provides four
signal pins that may be used to implement this
interface directly for an external keyboard and
mouse.
Hard Powerdown Mode
This mode is entered by executing a STOP
instruction. The oscillator is stopped by
disabling the oscillator driver
either RESET is driven active or a data byte is
written to the DBBIN register by master
CPU, this mode will be exited (as above).
However, as the oscillator cell will require an
initialization time, either RESET must be held
active for sufficient time to allow the oscillator to
stabilize. Program execution will resume as
above.
cell. When
The FDC37C93xFR has four high-drive, open-
drain output, bidirectional port pins that can be
used for external serial interfaces, such as ISA
external keyboard and PS/2-type mouse
interfaces. They are KCLK, KDAT, MCLK, and
MDAT. P26 is inverted and output as KCLK. The
KCLK pin is connected to TEST0. P27 is
inverted and output as KDAT. The KDAT pin is
connected to P10. P23 is inverted and output
as MCLK. The MCLK pin is connected to
TEST1. P22 is inverted and output as MDAT.
The MDAT pin is connected to P11. Note:
External pull-ups may be required.
a
INTERRUPTS
The FDC37C93xFR provides the two 8042
interrupts; IBF and the Timer/Counter Overflow.
KEYBOARD POWER MANAGEMENT
MEMORY CONFIGURATIONS
The keyboard provides support for two power-
saving modes: soft powerdown mode and hard
powerdown mode. In soft powerdown mode,
the clock to the ALU is stopped but the
timer/counter and interrupts are still active. In
hard power down mode the clock to the 8042 is
The FDC37C93xFR provides 2K of on-chip
ROM and 256 bytes of on-chip RAM.
Register Definitions
Host I/F Data Register
stopped.
Efforts must be made to reduce
power wherever possible!
The Input Data register and Output Data register
are each 8 bits wide. A write to this 8 bit register
will load the Keyboard Data Read Buffer, set the
OBF flag and set the KIRQ output if enabled. A
read of this register will read the data from the
Keyboard Data or Command Write Buffer and
clear the IBF flag. Refer to the KIRQ and Status
register descriptions for more information.
Soft Powerdown Mode
This mode is entered by executing a HALT
instruction. The execution of program code is
halted until either RESET is driven active or a
data byte is written to the DBBIN register by a
master CPU. If this mode is exited using the
137
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