Table 87 - CR09: ADRx Upper Address Decoder and Configuration
D7
D6
D5
D4
D3
D2
D1
D0
ADRx
Reserved
ADRA11
ADRA10
ADRA9
ADRA8
CONFIGURATION
CONTROL
Table 88 - ADRx Configuration Bits
ADRx
CONFIGURATION
CONTROL
DESCRIPTION
D7
0
0
D6
0
1
ADRx disabled
1 Byte decode
A[3:0]=0000b
1
1
0
1
8 Byte block decode
A[3:0]=0XXXb
16 byte block decode
A[3:0]=XXXXb
CR0A
CR0A can only be accessed in the configuration state and after the CSR has been initialized to 0AH. The default
value of this register after power up is 00H (Table 88). CR0A defines the FIFO threshold for the ECP mode parallel
port. Bits D[5:4] are Reserved. Reserved Bits cannot be written and return 0 when read. Bits D[7:6] are the IR
OUTPUT MUX bits (Table 89) and are reset to the default state by a POR or a hardware reset.
Table 89 - CR0A
D7
D6
D5
D4
D3
D2
ECP FIFO THRESHOLD
THR2 THR1
D1
D0
IR OUTPUT MUX
(see Table 90)
RESERVED
THR3
THR0
Table 90 - CR0A: IR OUTPUT MUX Bits
D7
0
D6
0
Mux Mode
Active device to COM port (Default). That is, use pins IRRX and IRTX (pins
88 and 89).
0
1
1
1
0
1
Active device to IR port. That is, use IRRX2, IRTX2 (pins 23, 24).
Reserved.
Outputs Inactive: IRTX and IRTX2 are High-Z.
Note: The function of the IR OUTPUT MUX bits and how they are reset has been modified from the FDC37C669.
The first two options were previously selected through CR04.
CR0B
CR0B can only be accessed in the configuration state and after the CSR has been initialized to 0BH. The default
value of this register after power up is 00H (Table 91). CR0B indicates the Drive Rate table used for each drive (see
Table 20). Refer to section CR1F on page 108 for the Drive Type register.
Table 91 - CR0B
FDD3
FDD2
FDD1
FDD0
D7
D6
D5
D4
D3
D2
D1
D0
DRT1
DRT0
DRT1
DRT0
DRT1
DRT0
DRT1
DRT0
SMSC DS – FDC37N3869
Page 104
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
