CR02
CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. The default
value of this register after power up is 88H (Table 79).
Table 79 - CR02
BIT NO.
BIT NAME
Reserved
DESCRIPTION
0:2
3
Read Only. A read returns “0”.
UART1 Power Down1 A high level on this bit, allows normal operation of the Primary
Serial Port (Default). A low level on this bit places the Primary
Serial Port into Power Down Mode.
4:6
7
Reserved
Read Only. A read returns “0”.
UART2 Power Down1 A high level on this bit, allows normal operation of the
Secondary Serial Port, including the SCE/FIR block (Default).
A low level on this bit places the Secondary Serial Port
including the SCE/FIR block into Power Down Mode.
Note1: Power Down bits disable the respective logical device and associated pins, however the power down bit
does not disable the selected address range for the logical device. To disable the host address registers the
logical device’s base address must be set below 100h. Devices that are powered down but still reside at a
valid I/O base address will participate in Plug-and-Play range checking.
CR03
CR03 can only be accessed in the configuration state and after the CSR has been initialized to 03H. The default
value after power up is 70H (Table 80).
Table 80 - CR03
BIT NO.
BIT NAME
DESCRIPTION
0
PWRGD/
GAMECS
Bit 0
0
1
Pin function
PWRGD (default)
GAMECS
1
Enhanced Floppy
Mode 2
Floppy Mode - Refer to the description of the TAPE
DRIVE REGISTER (TDR) for more information on
these modes.
Bit 1
0
1
NORMAL Floppy Mode (Default)
Enhanced Floppy Mode 2 (OS2)
3
4
Reserved
DRVDEN1
Reserved - Read as zero
Bit 4
Pin DRVDEN1 Output1
0
1
Output Programmed DRVDEN1 Value
Force DRVDEN1 Output High (default)
5
6
MFM
IDENT is used in conjunction with MFM to define the FDC
interface mode.
IDENT
IDENT
MFM
MODE
1
1
1
0
1
0
AT Mode (Default)
Reserved
PS/2
0
0
Model 30
7,2
nADRx/nCLKRUN
Bit - 7 Bit - 2
Pin 92 (TQFP)
0
1
1
x
0
1
Reserved2
nADRX
nCLKRUN
Note1: See NOTE2 in section CR05 on page 102.
Note2: Pin 92 (TQFP) is tri-stated at power-up.
SMSC DS – FDC37N3869
Page 100
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
