UART1
UART1 IRQ
OUT2 bit Output State OUT2 bit
UART2
UART2 IRQ
IRQ PINS
UART2
UART1
UART2
Share
IRQ
Yes
Yes
Yes
UART1
Output State
asserted
de-asserted
asserted
Pin State
Pin State
1
1
1
1
asserted
asserted
de-asserted
de-asserted
1
1
1
1
1
1
1
0
Z
Z
Z
Z
de-asserted
Yes
It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ number.
Potential damage to chip may result. Note: Z = Don’t Care.
CR29
CR29 can only be accessed in the configuration state and after the CSR has been initialized to 29H. The default
value of this register after power up is 00H (Table 111). CR29 controls the HPMODE bit and is used to select the IRQ
mapping (bits 0 - 3) for the IRQIN pin. Refer to IRQ encoding for CR27 (Table 109). Any unselected IRQ output
(registers CR27 - CR29) is in tristate.
Table 111 - CR29
BIT NO.
NAME
IRQIN
HPMODE
DESCRIPTION
Selects the IRQ for IRQIN
See
0-3
4
0
1
Select IRMODE (default)
Select IRR3
5-7
RESERVED
Not Writeable, Reads Return “0”
CR2A
Register CR2A is reserved. The default value of this register after power up is 00H.
CR2B
CR2B can only be accessed in the configuration state and after the CSR has been initialized to 2BH. The default
value of this register after power up is 00H (Table 112). CR2B is used to set the SCE (FIR) base address ADR[10:3].
The SCE base address can be set to 224 locations on 8-byte boundaries from 100H - 7F8H. To disable the SCE,
set ADR10, ADR9 and ADR8 to zero.
SCE Address Decoding: nCS = ’0’ required to access SCE registers. A[2:0] are decoded as XXXb.
Table 112 - CR2B: SCE (FIR) Base Address Register
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADR10
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
SMSC DS – FDC37N769
Page 111 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
