CR26
CR26 can only be accessed in the configuration state and after the CSR has been initialized to 26H. The default
value of this register after power up is 00H (Table 108). CR26 is used to select the DMA for the FDC (Bits 4 - 7) and
the Parallel Port (bits 0 - 3). Any unselected DMA Requset output (DRQ) is in tristate.
Table 108 - CR26: FDC and PP DMA Selection Register
D3-D0 or D7-D4
0000
DMA SELECTED
None
0001
DMA_A
0010
DMA_B
0011
DMA_C
CR27
CR27 can only be accessed in the configuration state and after the CSR has been initialized to 27H. The default
value of this register after power up is 00H (Table 109). CR27 is used to select the IRQ for the FDC (Bits 4 - 7) and
the Parallel Port (bits 3 - 0). Any unselected IRQ output (registers CR27 - CR29) is in tristate.
Table 109 - CR27: FDC and PP IRQ Selection Register
D3-D0 or D7-D4
0000
IRQ SELECTED
None
0001
IRQ_A
0010
IRQ_B
0011
IRQ_C
0100
IRQ_D
0101
IRQ_E
0110
IRQ_F
0111
1000
Reserved
IRQ_H
CR28
CR28 can only be accessed in the configuration state and after the CSR has been initialized to 28H. The default
value of this register after power up is 00H. CR28 is used to select the IRQ for Serial Port 1 (bits 7 - 4) and for Serial
Port 2 (bits 3 - 0). Refer to the IRQ encoding for CR27 (Table 109). Any unselected IRQ output (registers CR27 -
CR29) is in tristate.
To properly share an IRQ between UART1 and UART2:
1. Configure UART1 to use the desired IRQ pin.
2. Set UART2 to 0FH i.e., set CR28.[3:0] = 1111b. This selects the share IRQ mechanism. Refer to Table
110, below.
Table 110 - UART Interrupt Operation
UART1
UART1 IRQ
OUT2 bit Output State OUT2 bit
UART2
IRQ PINS
UART2
UART1
UART2
UART2 IRQ
Output State
Share
IRQ
No
No
No
No
No
No
No
UART1
Pin State
Pin State
0
1
1
0
0
1
1
1
1
0
1
1
0
0
Z
asserted
de-asserted
Z
0
0
0
1
1
1
1
1
1
0
0
0
1
1
Z
Z
Z
Z
1
0
Z
Z
1
1
0
0
Z
1
0
1
0
Z
Z
Z
1
0
1
0
1
0
Z
Z
Z
Z
Z
asserted
de-asserted
asserted
de-asserted
asserted
de-asserted
Z
Z
asserted
asserted
de-asserted
de-asserted
Z
asserted
de-asserted
Z
No
No
Yes
Yes
Yes
Yes
Yes
Z
Z
asserted
de-asserted
Z
SMSC DS – FDC37N769
Page 110 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
