UF
b3-0
The update-ended interrupt flag bit is set after
each update cycle. When the UIE bit is also a
"1", the "1" in UF causes the IRQF bit to be set
and asserts IRQB. A RESET_DRV or a read of
Register C causes UF to be cleared.
The unused bits of Register C are read as zeros
and cannot be written.
REGISTER D (DH) - BITS[7,6] ARE READ-ONLY, BITS[5:0] ARE READ/WRITE
MSB
b7
VRT
LSB
b0
b6
0
b5
b4
b3
b2
b1
Date Alarm
VRT
b5:b0
When a "1", this bit indicates that the contents of
the RTC are valid. A "0" appears in the VRT bit
when the battery voltage is low. The VRT bit is a
read-only bit, which can only be set by a read of
Register D. Refer to Power Management for the
conditions when this bit is reset. The processor
program can set the VRT bit when the time and
calendar are initialized to indicate that the time is
valid.
Date Alarm; These bits store the date of month
alarm value. If set to 000000b, then a don’t care
state is assumed. The host must configure the
date alarm for these bits to do anything, yet they
can be written at any time. If the date alarm is
not enabled, these bits will return zeros. These
bits are not affected by RESET_DRV.
Note: Bits[6:0] are not accessible during an update
cycle.
b6
REGISTER 7E (7Eh) CONTROL REGISTER 1
Read as zero and cannot be written.
Default is 0; cleared upon Vbat POR. This
register is battery backed-up.
D7
XTAL_
CAP
D6
0
D5
0
D4
0
D3
0
D2
VTR_POR VTR_POR AL_REM_
_EN _OFF EN
D1
D0
145
SMSC [ SMSC CORPORATION ]
