Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
See Figure 5.1 Interrupt Control on page 22.
7.2.31
Register 81h: TACH_PWM Association Register
Register
Address
Read/
Write
Bit 7
Bit 0
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSb)
(LSb)
81h
R/W
TACH_PWM Association
T4H
T4L
T3H
T3L
T2H
T2L
T1H
T1L
A4h
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to associate a PWM with a tachometer input. This association is used by the fan
logic to determine when to prevent a bit from being set in the interrupt status registers.
The fan tachometer will not cause a bit to be set in the interrupt status register:
a. if the current value in Current PWM Duty registers is 00h or
b. if the fan is disabled via the Fan Configuration Register.
Note: A bit will never be set in the interrupt status for a fan if its tachometer minimum is set to FFFFh.
See bit definition below.
Bits[1:0] Tach1. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[7:6] Tach4. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[1:0], Bits[3:2], Bits[5:4], Bits[7:6]
PWM Associated With Tachx
00
01
10
11
PWM1
PWM2
PWM3
Reserved
Notes:
■
Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1.
■
All TACH inputs must be associated with a PWM output. If the tach is not being driven by the
associated PWM output it should be configured to operate in Mode 1 and the associated TACH
interrupt must be disabled.
7.2.32
Register 82h: Interrupt Enable 3 Register
Register
Address
Read/
Write
Register
Name
Bit 7
Bit 0
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSb)
(LSb)
82h
R/W
Interrupt Enable 3 (Temp)
RES
RES
RES
RES
D2EN
D1EN
AMB
TEMP
0Eh
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to enable individual thermal error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group thermal enable bit (Bit[0] TEMP),
SMSC EMC6D102
Revision 0.4 (04-05-05)
DATA7S1HEET
SMSC [ SMSC CORPORATION ]
