A0-A2
nCS
VALID
t1
t2
t4
t3
t5
nRD
t6
t7
D0-D7
VALID DATA
min
Parameter
max
units
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
t1
t2
t3
t4
t5
t6
15
10
5**
0
nS
nS
nS
nS
nS
nS
4T*
40
20
t7
nRD High to Data High Impedance
0
nS
*
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
T is twice XTAL1 period if SLOW ARB = 1
nCS may become active after control becomes active, but the access time
**
will now be 45nS measured from the leading edge of nCS.
Note 1:
The Microcontroller typically accesses the COM20020-5 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020-5 cycles.
FIGURE 12 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
48
SMSC [ SMSC CORPORATION ]
