A0-A2
nCS
VALID
t1
t2
t4
t7
t3
t5
DIR
t6
nDS
t8
t9
D0-D7
VALID DATA
min
Parameter
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
max
units
t1
t2
t3
t4
t5
15
10
5**
0
10
nS
nS
nS
nS
nS
t6
t7
t8
t9
Cycle Time (nDS Low to Next Time Low)
nDIR Hold from nDS Active
nDS Low to Valid Data
4T*
10
nS
nS
nS
nS
40
20
nDS High to Data High Impedence
0
*
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
T is twice XTAL1 period if SLOW ARB = 1
**
nCS may become active after control becomes active, but the access time will
now be 45nS measured from the leading edge of nCS.
The Microcontroller typically accesses the COM20020-5 on every other cycle.
Note 1:
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020-5 cycles.
FIGURE 12A - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ
CYCLE
49
SMSC [ SMSC CORPORATION ]
