AD0-AD2,
D3-D7
VALID
t3
VALID DATA
t1
t2,
t4
nCS
ALE
nDS
t6
t7
t5
t8
t9
t10
DIR
Parameter
min
max
units
t1
t2
t3
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
30
10
10
20
15
t4 nCS Hold from ALE Low
t5 ALE Low to nDS Low
t6 nDS Low to Valid Data
t7 nDS High to Data High Impedance
t8 Cycle Time (nDS Low to Next Time Low)
t9 DIR Setup to nDS Active
40
20
0
4T*
10
t10 DIR Hold from nDS Inactive
10
*
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
T is twice XTAL1 period if SLOW ARB = 1
Note 1:
The Microcontroller typically accesses the COM20020-5 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020-5 cycles.
FIGURE 10 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE
44
SMSC [ SMSC CORPORATION ]
