AD0-AD2,
D3-D7
VALID
t3
VALID DATA
t1
t2,
t4
nCS
ALE
nRD
t6
t7
t5
t8
Parameter
max
units
min
t1
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nRD Low
nRD Low to Valid Data
nRD High to Data High Impedance
Cycle Time (nRD Low to Next Time Low)
nS
nS
nS
nS
nS
nS
nS
nS
30
10
10
20
15
t2
t3
t4
t5
t6
t7
t8
40
20
0
4T*
*
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
T is twice XTAL1 period if SLOW ARB = 1
Note 1:
The Microcontroller typically accesses the COM20020-5 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020-5 cycles.
FIGURE 10A - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
45
SMSC [ SMSC CORPORATION ]
