AD0-AD2,
D3-D7
VALID
VALID DATA
t1
t2,
t4
nCS
t3
ALE
t7
t5
t6
nWR
Note 2
t8**
t8
Parameter
min
max
units
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nWR Low
Valid Data Setup to nWR High
Data Hold from nWR High
Cycle Time (nWR Low to Next Time Low)**
t1
t2
t3
t4
t5
t6
t7
t8
nS
nS
nS
nS
nS
nS
nS
nS
30
10
10
20
15
30
10
4T*
*
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
T is twice XTAL1 period if SLOW ARB = 1
The Microcontroller typically accesses the COM20020-5 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020-5 cycles.
Note 1:
**
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4T from the trailing edge of nWR to the leading edge of the
next nWR.
Note 2:
FIGURE 11A - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE
47
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