A0-A2
VALID
t1
t2
t7
nCS
DIR
t4
t3
t5
t6
nDS
Note 2
t6**
t8
t9
D0-D7
VALID DATA
Parameter
min
15
10
5
max
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
t1 Address Setup to nDS Active
t2 Address Hold from nDS Inactive
t3 nCS Setup to nDS Active
t4 nCS Hold from nDS Inactive
t5 DIR Setup to nDS Active
t6 Cycle Time (nDS Low to Next Time Low)**
t7 DIR Hold from nDS Inactive
t8 Valid Data Setup to nDS High
t9 Data Hold from nDS High
0
10
4T*
10
30**
10
*
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
T is twice XTAL1 period if SLOW ARB = 1
**nCS may become active after control becomes active, but the data setup time will
now be 30 nS measured from the later of nCS falling or Valid Data available.
Note 1: The Microcontroller typically accesses the COM20020-5 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020-5 cycles.
Note 2:
Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4T from the trailing edge of nDS to the leading
edge of the next nDS.
FIGURE 13A - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE
CYCLE
51
SMSC [ SMSC CORPORATION ]
