AD0-AD2,
D3-D7
VALID
t3
VALID DATA
t1
t2,
t4
nCS
ALE
nDS
t7
t5
t6
Note 2
t8**
t8
DIR
t9
Parameter
t10
min
max
units
t1
t2
t3
t4
t5
t6
t7
t8
t9
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High
Cycle Time (nDS Low to Next Time Low)**
DIR Setup to nDS Active
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
30
10
10
20
15
30
10
4T*
10
10
DIR Hold from nDS Inactive
t10
*
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
T is twice XTAL1 period if SLOW ARB = 1
The Microcontroller typically accesses the COM20020-5 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020-5 cycles.
Note 1:
**
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4T from the trailing edge of nDS to the leading edge of the
next nDS.
Note 2:
FIGURE 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
46
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