Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 7.28 Wakeup Mask Register 2
N/A
HOST
ADDRESS
0x7F2D
8051
ADDRESS
VCC1
0x00
POWER
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST
TYPE
R
R
R
R
R
R/W
R/W
R
8051 R/W
Reserved
Reserved Reserved Reserved Reserved HTIMER WK_
Reserved
timeouts ANY
KEY
BIT NAME
asserted
Note 7.33 When set ‘1’, a bit in this register masks the corresponding bit in Table 7.21, "Wakeup
Source Register 2". Reserved bits are logic zero read only.
Table 7.29 Wakeup Mask Register 4
N/A
HOST
ADDRESS
0x7F5A
8051
ADDRESS
VCC1
0x00
POWER
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
WK_SE
07
WK_SE
06
Reserved
WK_SE
04
WK_SE0 WK_SE
02
Reserved
Reserved
BIT NAME
3
Note 7.34 When set ‘1’, a bit in this register masks the corresponding bit in Table 7.22, "Wakeup
Source Register 4".
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA7S5HEET
SMSC [ SMSC CORPORATION ]
