Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 7.24 Wakeup Source Register 6
N/A
HOST
ADDRESS
0x7F63
VCC1
0x00
8051 ADDRESS
POWER
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 TYPE
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
WK_SE2 WK_SE2 WK_SE2 WK_SE2 WK_SE2 WK_SE2 WK_SE2 WK_SE2
BIT NAME
7
6
5
4
3
2
1
0
asserted
asserted
asserted
asserted
asserted
asserted
asserted
asserted
Note 7.29 The interrupt source bits in this register are cleared by a writing a “1” to the bit. When an
interrupt source is asserted, a read from the corresponding bit in this register is a logic ‘1’.
Table 7.25 Wakeup Source Register 7
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F64
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 TYPE
R
R
R/WC
R
R
R
R/WC
R/WC
Reserved
SPIDONE Reserved
FAN
FAN
BIT DESCRIPTION
TACH2
TACH1
Note 7.30 The interrupt source bits in this register are cleared by a writing a “1” to the bit. When an
interrupt source is asserted, a read from the corresponding bit in this register is a logic ‘1’.
Reserved bits are logic zero read only.
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA7S3HEET
SMSC [ SMSC CORPORATION ]
