Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 7.36 Edge Selection
D7:6
D5:4
INTERRUPT ASSERTION
D3:2
D1:0
00
01
10
11
EDGE HIGH TO LOW
EDGE LOW TO HIGH
EITHER EDGE
RESERVED
Table 7.37 Edge Select 4B
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F58
VCC1
0x00
DEFAULT
BIT
D7:6
D5:4
D3:2
D1:0
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R/W
R/W
R
R/W
SE07 Select
SE06 Select
Reserved
SE04 Select
USER’S NOTE: Edge-generated interrupts may occur from a change in the edge select bits.
Refer to Table 7.36, "Edge Selection".
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA7S9HEET