Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 7.22 Wakeup Source Register 4
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F59
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 TYPE
R/WC
R/WC
R
R/WC
R/WC
R/WC
R
R
WK_SE0 WK_SE0 Reserved WK_SE0 WK_SE0 WK_SE0 Reserved Reserved
BIT DESCRIPTION
7
6
4
3
2
asserted asserted
asserted
asserted asserted
Note 7.27 The interrupt source bits in this register are cleared by a writing a “1” to the bit. When an
interrupt source is asserted, a read from the corresponding bit in this register is a logic ‘1’.
Table 7.23 Wakeup Source Register 5
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F5E
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 TYPE
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
WK_SE17
asserted
WK_SE1 WK_SE1 WK_SE1 WK_SE1 WK_SE1 WK_SE1 WK_SE
10
asserted asserted asserted asserted
BIT DESCRIPTION
6
5
4
3
2
1
asserted asserted asserted
Note 7.28 The interrupt source bits in this register are cleared by a writing a “1” to the bit. When an
interrupt source is asserted, a read from the corresponding bit in this register is a logic ‘1’.
Revision 1.1 (01-14-03)
SMSC LPC47N350
DATA7S2HEET
SMSC [ SMSC CORPORATION ]
