Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
B7
B6
B5
B4
B3
B2
B1
B0
IRQF
PF
AF
UF
0
0
0
0
IRQF
The interrupt request flag is set to a "1" when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
Any time the IRQF bit is a "1", the IRQB signal is driven low. All flag bits are cleared after Register
C is read or by the VCC1 POR port.
PF
The periodic interrupt flag is a read only bit which is set to a "1" when a particular edge is detected on
the selected tap of the divider chain. The RS3 -RS0 bits establish the periodic rate. PF is set to a "1"
independent of the state of the PIE bit. PF being a "1" sets the IRQF bit and initiates an IRQB signal
when PIE is also a "1". The PF bit is cleared by VCC1 POR or by a read of Register C.
AF
The alarm interrupt flag when set to a "1" indicates that the current time has matched the alarm time.
A "1" in AF causes a "1"to appear in IRQF and the IRQB port to go low when the AIE bit is also a "1".
A VCC1 POR or a read of Register C clears the AF bit.
UF
The update-ended interrupt flag bit is set after each update cycle. When the UIE bit is also a "1", the
"1" in UF causes the IRQF bit to be set and asserts IRQB. A VCC1 POR or a read of Register C
causes UF to be cleared.
b3-0
The unused bits of Register C are read as “0” and cannot be written.
23.7.4 Register D
MSB
LSB
b7
b6
0
b5
b4
b3
b2
b1
B0
VRT
Day of month
VRT
The Valid RAM and Time (VRT) bit is cleared by VCC0 (Vbat) POR, only. This is the only case where
the contents of the RAM, as well as the time and calendar registers, are not valid. The VRT bit can only
be set by a read of Register D. The 8051 can set the VRT bit reading Register D after both of the
following condition are met: VCC1_PWRGD =1 and the 8051 completes initialization. The Host can set
the VRT bit reading Register D after PWRGD =1 See Section 23.11, "Power Management".
b6
Read as zero and cannot be written.
b5:b0
Revision 1.1 (01-14-03)
264
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
