Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
23.8.2 Periodic Interrupt Selection
The periodic interrupt allows the IRQB port to be triggered from once every 500 ms to once every 122.07
µs. As Table 23.7 shows, the periodic interrupt is selected with the RS0-RS3 bits in Register A. The
periodic interrupt is enabled with the PIE bit in Register B.
23.9
8051 RTC CMOS access
The LPC47N350FR implements an interface that allows the 8051 to read/write the RTC and CMOS
registers under the following conditions: When nRESET_OUT is active, or when VCC2 is off, or by use
of the smart host protocol.
RTCCNTRL (RTC Control) Register
N/A
HOST
0x7FF5
VCC1
0x80
8051
POWER
DEFAULT
The RTC Control register is mirrored in CMOS register 0x7Fh in both bank0 and bank1.
D7
D6
D5
D4
D3
D2
D1
D0
nSH
0
0
0
KREQH
HREQH
KREQL
HREQL
nSH
nSmart Host - This bit is controlled by the 8051. When set to a “1”, the host is not a smart host and
does not recognize the sharing protocol. When set to a “0”, the host is smart and can recognize the
sharing protocol. When set to “1”, this bit will clear HREQH and HREQL. Clearing this bit to “0” will
allow the 8051 to regain access to the CMOS RAM.
KREQL
Keyboard Request Low - The 8051 can set this bit when HREQL IS '0'. If the request is not granted,
this bit is read back as a zero and the request must be tried again.
Note: After regaining control of the CMOS, the 8051 must re-write the RTC Low Address Register
before accessing the RTC Data Register. This bit selects access to the CMOS RAM Addresses
0-7F.
HREQL
Host Request Low - This bit can be set by the host when KREQL is “0”. If the request is not granted,
this bit is read back as a “0” and the request must be tried again.
KREQH
Keyboard Request High - This bit can be set by the 8051 when HREQH is “0” If the request is not
granted, this bit is read back as a “0” and the request must be tried again. Note: After regaining control
of the CMOS, the 8051 must re-write the RTC High Address Register before accessing the RTC Data
Register. This bit selects access to the CMOS RAM Addresses 80-FF.
HREQH
Host Request High - This bit can be set by the host when KREQH is “0”. If the request is not granted,
this bit is read back as a “0” and the request must be tried again.
Revision 1.1 (01-14-03)
266
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
