Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Day of month Alarm; these bits store the day of month alarm value. If set to 000000b, then a don’t care
state is assumed. The host must configure the Day of month alarm for these bits to do anything, yet
they can be written at any time. If the Day of month alarm is not enabled, these bits will return zeros.
These bits are not affected by RESET_DRV, VCC1_POR or VCC2_POR. The BCD Range for the Day
of month of month alarm is 1-31 and the Binary Range is 01-1F.
23.7.5 Century Byte
The century byte is located at RTC/Bank0 register 0x32. The century byte is incremented by one when
the year byte changes from 99 or 0x63 to 0. The BCD Range for the century byte is 00-99 and the
Binary Range is 00-63.
23.7.6 General Purpose
Registers 0xEh-0x7EH, except 0x32 (The Century Byte) in Bank0 and 0x0-0x7E in Bank1 are general
purpose "CMOS" registers. These registers can be used by the host or 8051 and are fully available
during the time update cycle. The contents of these registers are preserved by VCC0 power. Registers
Eh-7Eh are in bank0 and registers 80h-FEh are in bank1.
23.7.7 Shared RTC Control
Each bank’s last addressable location (0x7F) accesses the Shared RTC Control. The Shared RTC
Control Register implements an interface that allows the 8051 to read/write the RTC and CMOS
registers by use of the smart host protocol. Refer to 8051 RTC CMOS access, Section 23.9, "8051 RTC
CMOS access," on page 266 for the definition of this register.
23.8
Interrupts
The RTC includes three separate fully automatic sources of interrupts to the processor. The alarm
interrupt may be programmed to occur at rates from one-per-second to one-a-day. The periodic interrupt
may be selected for rates from half-a-second to 122.070 ms. The update ended interrupt may be used
to indicate to the program that an update cycle is completed. Each of these independent interrupts are
described in greater detail in other sections.
The processor program selects which interrupts, if any, it wishes to receive by writing a "1" to the
appropriate enable bits in Register B. A "0" in an enable bit prohibits the IRQB port from being asserted
due to that interrupt cause. When an interrupt event occurs a flag bit is set to a "1" in Register C, which
are set independent of the state of the corresponding enable bits in Register B. Each of the three
interrupt sources have separate flag bits in Register C. The flag bits may be used with or without
enabling the corresponding enable bits. The flag bits in Register C are cleared (record of the interrupt
event is erased) when Register C is read. Double latching is included in Register C to ensure the bits
that are set are stable throughout the read cycle. All bits which are high when read by the program are
cleared, and new interrupts are held until after the read cycle. If an interrupt flag is already set when
the interrupt becomes enabled, the IRQB port is immediately activated, though the interrupt initiating the
event may have occurred much earlier.
When an interrupt flag bit is set and the corresponding interrupt-enable bit is also set, the IRQB port is
driven low. IRQB is asserted as long as at least one of the three interrupt sources has its flag and enable
bits both set. The IRQF bit in Register C is a "1" whenever the IRQB port is being driven low.
23.8.1 Frequency Divider
The RTC has 22 binary divider stages following the clock input. The output of the divider is a one Hertz
signal to the update-cycle logic. The divider is controlled by the three divider bits (DV3-DV0) in Register
A. As shown in Table 23.6 the divider control bits can select the operating mode, or be used to hold
the divider chain reset that allows precision setting of the time. When the divider chain is changed from
reset to the operating mode, the first update cycle is one-half second later.
SMSC LPC47N350
265
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
