Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
The 12/24 bit in Register B establishes whether the hour locations represent 1 to 12 or 0 to 23. The
12/24 bit cannot be changed without reinitializing the hour locations. When the 12 hour format is
selected, the high order bit of the hours byte represents PM when it is a "1".
Once per second, the twelve time, calendar and alarm registers are updated, Incrementing by one
second and checking for an alarm condition. During the update cycle all the registers in Table 23.4,
except Register D, are not accessible by the processor program. The update cycle time is shown in
Table 23.2. The update logic contains circuitry for automatic end-of-month recognition as well as
automatic leap year compensation.
The three alarm registers may be used in two ways. First, when the program inserts an alarm time in
the appropriate hours, minutes and seconds alarm locations, the alarm interrupt is initiated at the
specified time each day if the alarm enable bit is high. The second usage is to insert a "don't care” state
in one or more of three alarms registers. The "don't care" code is any hexadecimal byte from C0 to FF
inclusive. That is the two most significant bits of each byte, when set to "1" create a "don't care"
situation. An alarm interrupt each hour is created with a "don't care" code in the hours alarm location.
Similarly, an alarm is generated every minute with "don't care" codes in the hours and minutes alarm
bytes. The "don't care" codes in all three alarm bytes create an interrupt every second.
Table 23.4 RTC Register Valid Range
BCD
BINARY
RANGE
ADD
REGISTER FUNCTION
Register 0: Seconds
RANGE
0
1
2
3
4
00-59
00-59
00-3B
00-3B
00-3B
00-3B
01-0C
81-8C
00-17
01-0C
81-8C
00-17
01-07
01-1F
01-0C
00-63
01-1F
Register 1: Seconds Alarm
Register 2: Minutes
Register 3: Minutes Alarm
Register 4: Hours
00-59
00-59
01-12 am
81-92 pm
00-23
(12 hour mode)
(24 hour mode)
5
Register 5: Hours Alarm
(12 hour mode)
01-12 am
81-92 pm
00-23
(24 hour mode)
6
7
Register 6: Day of Week
Register 7: Day of Month
Register 8: Month
Register 9: Year
01-07
01-31
8
01-12
9
00-99
D
32
Day of Month Alarm
Century Byte
01-31
00-99
00-63
23.6
Update Cycle
An update cycle is executed once per second if the SET bit in Register B is clear and the DV0-DV2
divider is not clear. The SET bit in the "1" state permits the program to initialize the time and calendar
registers by stopping an existing update and preventing a new one from occurring.
The primary function of the update cycle is to increment the seconds register, check for overflow,
increment the minutes register when appropriate and so forth through to the year of the century byte.
Revision 1.1 (01-14-03)
260
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
