Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Chapter 22 ACPI PM1 Block
22.1
ACPI PM1 Block Overview
The LPC47N350 supports ACPI as described in this section. These features comply with the ACPI
Specification, Revision 1.0/2.0, through a combination of hardware and 8051 software.
The LPC47N350 implements the ACPI fixed registers but includes only those bits that apply to the power
button sleep button and RTC alarm events. The ACPI WAK_STS, SLP_TYPx, and SLP_EN bits are
also supported.
The registers in the LPC47N350 ACPI PM1 Block occupy eight addresses in the host I/O space and
are specified as offsets from the ACPI PM1 Block base address. The ACPI PM1 Block base address
is relocatable depending on the values programmed in LPC47N350 configuration registers CR60 and
CR61 in Logical Device Number 1.
The functions described in the following sub-sections can generate a SCI event on the nEC_SCI pin.
In the LPC47N350, an SCI event is considered the same as an ACPI wakeup or runtime event. The
8051 can also generate a SCI on the nEC_SCI pin by setting the 8051_SCI_STS bit in the
8051_PM_STS register (see Section 22.6, "nEC_SCI Pin Interface").
22.2
ACPI PM1 Block SCI Event-Generating Functions
Power Button With Override
The power button has a status and an enable bit in the PM1_BLK of registers to provide an SCI upon
the button press. The status bit is software Read/Writeable by the 8051; the enable bit is Read-only by
the 8051. It also has a status and enable bit in the PM1_BLK of registers to indicate and control the
power button override (fail-safe) event. These bits are not required by ACPI. The power button override
event status bit is software Read/Writeable by the 8051; the enable bit is software read-only by the 8051.
The enable bit for the override event is located at bit 1 in the PM1_CNTRL2 register.
The power button enable bit is set by the Host to enable the generation of an SCI due to the power
button event. The status bit is set by the 8051 when it generates a power button event and is cleared
by the Host writing a ‘1’ to this bit (writing a ‘0’ has no effect); it can also be cleared by the 8051. If
the enable bit is set, the 8051 will generate an SCI power management event.
Sleep Button
The sleep button has a status and an enable bit in the PM1_BLK of registers to provide an SCI upon
the button press. The status bit is software Read/Writeable by the 8051; the enable bit is Read-only by
the 8051.
The sleep button enable bit is set by the Host to enable the generation of an SCI due to the sleep button
event. The status bit is set by the 8051 when it generates a sleep button event and is cleared by the
Host writing a ‘1’ to this bit (writing a ‘0’ has no effect); it can also be cleared by the 8051. If the enable
bit is set, the 8051 will generate an SCI power management event.
RTC Alarm
The ACPI specification requires that the RTC alarm generate a hardware wake-up event from the
sleeping state. The RTC alarm can be enabled as an SCI event and its status can be determined
through bits in the PM1_BLK of registers. The status bit is software Read/Writeable by the 8051; the
enable bit is Read-only by the 8051.
The RTC enable bit is set by the Host to enable the generation of an SCI due to the RTC alarm event.
The status bit is set by the 8051 when the RTC generates an alarm event and is cleared by the Host
writing a ‘1’ to this bit (writing a ‘0’ has no effect); it can also be cleared by the 8051. If the enable bit
is set, the 8051 will generate an SCI power management event.
SMSC LPC47N350
249
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
