Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Host Attribute:
8051 Attribute:
Size:
Read/Write
Read
8-bits
An interrupt is generated to the 8051 when the Host writes this to register.
Table 22.6 Power Management 1 Enable Register 2
BIT
NAME
DESCRIPTION
0
1
2
PWRBTN_EN
SLPBTN_EN
RTC_EN
This bit can be read or written by the Host. It can be read by the 8051.
This bit can be read or written by the Host. It can be read by the 8051.
This bit can be read or written by the Host. It can be read by the 8051.
Reserved bits cannot be written and return “0” when read.
3-7
RESERVED
22.5.5 Power Management 1 Control Register 1 (PM1_CNTRL 1)
Host Register Location:
8051 Register Location:
Default Value:
<ACPI PM1 Block Base Address>+4 System I/O Space
n/a
00h on VCC1 POR
Host Attribute:
Read
8-bits
Size:
Table 22.7 Power Management 1 Control Register 1
BIT
NAME
DESCRIPTION
0-7
Reserved
Reserved bits cannot be written and return “0” when read.
22.5.6 Power Management 1 Control Register 2 (PM1_CNTRL 2)
Host Register Location:
8051 Register Location:
Default Value:
<ACPI PM1 Block Base Address>+5 System I/O Space
0x7F82
00h on VCC1 POR
Read/Write
Host Attribute:
8051 Attribute:
Size:
Read. Note: Bit 5 is Read/Write
8-bits
An interrupt is generated to the 8051 when the Host writes to this register.
Table 22.8 Power Management 1 Control Register 2
BIT
NAME
Reserved
DESCRIPTION
Reserved. This field always returns zero.
0
1
PWRBTNOR_EN
SLP_TYPx
This bit can be set or cleared by the Host, read by the 8051.
These bits can be set or cleared by the Host, read by the 8051.
2-4
SMSC LPC47N350
253
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
