Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
called out specifically, and the respective enable bit in the enable register is marked as reserved for
these special cases.
■
The enable registers allow the setting of the status bit to generate an interrupt (under 8051 control).
As a general rule, there is an enable bit in the enable register for every status bit in the status
register. The control register provides special controls for the associated event, or special control
features that are not associated with an interrupt event. The order of a register block is the status
registers, followed by enable registers, followed by control registers.
22.5
Registers
The registers in the LPC47N350 ACPI PM1 Block occupy eight addresses in the host I/O space and
are specified as offsets from the ACPI PM1 Block base address (Table 22.2).
The registers in the PM1 Block are powered by VCC1.
Table 22.2 ACPI PM1 Block Registers
SIZE
REGISTER
(BITS)
OFFSET
ADDRESS
PM1_STS 1
PM1_STS 2
PM1_EN 1
PM1_EN 2
8
0
1
2
3
4
5
6
7
<ACPI PM1 Block Base Address>
<ACPI PM1 Block Base Address>+1h
<ACPI PM1 Block Base Address>+2h
<ACPI PM1 Block Base Address>+3h
<ACPI PM1 Block Base Address>+4h
<ACPI PM1 Block Base Address>+5h
<ACPI PM1 Block Base Address>+6h
<ACPI PM1 Block Base Address>+7h
PM1_CNTRL 1
PM1_CNTRL 2
RESERVED
RESERVED
22.5.1 Power Management 1 Status Register 1 (PM1_STS 1)
Host Register Location:
8051 Register Location:
Default Value:
<ACPI PM1 Block Base Address> System I/O Space
n/a
00h on VCC1 POR
Host Attribute:
Read
8-bits
Size:
Table 22.3 Power Management 1 Status Register 1
BIT
NAME
DESCRIPTION
0-7
Reserved
Reserved. These bits always return a value of zero.
22.5.2 Power Management 1 Status Register 2 (PM1_STS 2)
Host Register Location:
8051 Register Location:
Default Value:
<ACPI PM1 Block Base Address>+1h System I/O Space
0x7F80
00h on VCC1 POR
SMSC LPC47N350
251
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
