Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Host Attribute:
8051 Attribute
Size:
Read/Write (Note 1)
Read/Write
8-bits
Note: These bits are set/cleared by the 8051 directly i.e., writing ‘1’ sets the bit and writing ‘0’ clears
it. These bits can also be cleared by the Host software writing a one to this bit position and by
VCC1 POR. Writing a 0 by the Host has no effect.
An interrupt is generated to the 8051 when the Host writes to this register.
Table 22.4 Power Management 1 Status Register 2
BIT
NAME
DESCRIPTION
0
1
PWRBTN_STS
This bit can be set or cleared by the 8051 to simulate a Power button status if
the power is controlled by the 8051. The Host writing a one to this bit can also
clear this bit. The 8051 must generate the associated SCI interrupt under
software control.
SLPBTN_STS
This bit can be set or cleared by the 8051 to simulate a Sleep button status if
the sleep state is controlled by the 8051. The Host writing a one to this bit can
also clear this bit. The 8051 must generate the associated SCI interrupt under
software control.
2
3
RTC_STS
This bit can be set or cleared by the 8051 to simulate a RTC status. The Host
writing a one to this bit can also clear this bit. The 8051 must generate the
associated SCI interrupt under software control.
PWRBTNOR_STS
This bit can be set or cleared by the 8051 to simulate a Power button override
event status if the power is controlled by the 8051. The Host writing a one to
this bit can also clear this bit. The 8051 must generate the associated hardware
event under software control.
4-6
7
Reserved
Reserved. These bits always return a value of zero.
WAK_STS
This bit can be set or cleared by the 8051. The Host writing a one to this bit
can also clear this bit.
22.5.3 Power Management 1 Enable Register 1 (PM1_EN 1)
Host Register Location:
8051 Register Location:
Default Value:
<ACPI PM1 Block Base Address>+2 System I/O Space
n/a
00h on VCC1 POR
Host Attribute:
Read
8-bits
Size:
Table 22.5 Power Management 1 Enable Register 1
BIT
NAME
DESCRIPTION
0-7
Reserved
Reserved. These bits always return a value of zero.
22.5.4 Power Management 1 Enable Register 2 (PM1_EN 2)
Host Register Location:
8051 Register Location:
Default Value:
<ACPI PM1 Block Base Address>+3 System I/O Space
0x7F81
00h on VCC1 POR
Revision 1.1 (01-14-03)
252
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
