Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 17.6 8051 STP_CLK Register
MBX94h
N/A
HOST ADDRESS
8051 ADDRESS
POWER
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
R
R
R
R
R
R/W
IDLE
Reserved
STP_CLK
IDLE Bit – D7
When the IDLE bit is ‘0’, the 8051 is not in idle mode; when the IDLE bit is ‘1’, the 8051 is in idle mode.
The IDLE bit is read-only.
STP_CLK Bit – D0
When the STP_CLK bit is ‘1’, the 8051 clock is stopped only when the nRESET_OUT pin is deasserted;
when the STP_CLK bit is ‘0’, the 8051 clock can run. The STP_CLK bit is read/write. See Section
7.8.3.5, "Output Enable Register," on page 62.
SMSC LPC47N350
197
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
