Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
17.7
ESMI Registers
The host can enable/disable the SMI interrupts generated as a result of the 8051 writing to Mailbox
register 1. The host can read the ESMI source register to determine for the LPC47N350 Mailbox
interface was the cause of the SMI.
Table 17.7 ESMI Source Register
MBX96
N/A
HOST ADDRESS
8051 ADDRESS
POWER
VCC2
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
R
R
R/W
R
R
R
Reserved
8051_WR Reserved
8051_WR
This bit is set when a 8051-to-host mailbox has been written. This bit is cleared by a read of Mailbox
Register 1 (MBX83).
Table 17.8 ESMI Mask Register
MBX97
N/A
HOST ADDRESS
8051 ADDRESS
POWER
VCC2
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
R
R
R/W
R
R
R
Reserved
ESMI_MASK Reserved
ESMI_MASK
Setting this bit masks the 8051-to-host mailbox SMI.
Revision 1.1 (01-14-03)
198
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
