Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
After reading Mailbox Register 1, the system can clear the register to “00H” by a dummy write to inform
the 8051 that the register has been read.
Table 17.5 Mailbox Register 1 (8051-To-System)
0x83
0x7F09
VCC1
0x00
MAILBOX INDEX
8051 ADDRESS
POWER
DEFAULT
BIT
D7
D6
RC
D5
RC
D4
RC
D3
RC
D2
RC
D1
RC
D0
RC
MBX TYPE
(Note 17.5)
RC
R/W
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
8051 R/W
BIT NAME
Note 17.5 RC = Read-only register is cleared when written.
17.6
8051 Stop Clock Register
The LPC Host can use the STP_CLK bit to stop the 8051 clock, for example when the LPC Bus Flash
Program Access interface is used to update the 64k Embedded Flash.
Figure 17.2 illustrates the sequence the LPC Host must follow to stop the 8051 clock. The 8051
STP_CLK Register shown in Table 17.6 contains the STP_CLK bit.
SMSC LPC47N350
195
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
