Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 18.2 PWM2 Speed Control Summary
FREQUENCY MULTIPLIER BITS (Note 18.7)
PWM2
CLOCK
MULTI-
PLIER
BIT
00 (1X)
01 (2X)
10 (4X)
11 (8X)
PWM2
CLOCK
SELECT
0 BIT
PWM2
CLOCK
CONTROL
BIT
PWM2
CLOCK
SELECT
1 BIT
FOUT
FOUT
FOUT
FOUT
6-BIT
DUTY
(KHZ)
(KHZ)
(KHZ)
(KHZ)
CYCLE
CONTROL
(DCC)
DUTY
CYCLE
(%)
Note 18.
10
Note 18.
9
Note 18.1
1
Note 18.1
2
Note 18.
12
Note 18.
12
Note 18.1
2
Note 18.8
0
X
0
X
0
X
0
1
0
1
0
1
0
0 (low)
15.625
23.44
0 (low)
31.25
43.875
62.5
0 (low)
62.5
0 (low)
125
0
(DCC ÷
64)
1-63
× 100
93.75
125
187.5
250
1
31.25
46.875
0.1831
0.275
93.75
0.3662
0.55
187.5
0.7324
1.1
375
1
0
0
1
1.4648
2.2
0.366
0.7333
2
1.46664 2.93328
1
0.55
1.1
2.2
4.4
1
X
X
X
0 (high)
0 (high) 0 (high)
0 (high)
-
-
Note 18.8 This is PWM2 Speed Control register bit 0.
Note 18.9 This is PWM Control register Bit 7.
Note 18.10 This is PWM Control register Bit 6.
Note 18.11 This is PWM2 Speed Control register Bit 7.
Note 18.12 When the PWM2 Clock Control Bit = ‘0’, Clock Select 0 = Clock Select 1 = ‘1’, and the
Clock Multiplier Bit = ‘0’ (regardless of the Frequency Multiplier Bits selection), the frequency
tolerance is ± 10 Hz. For all other combinations, the F frequency tolerance is ± 5%.
out
Note 18.13 This is PWM0/PWM1/PWM3 Frequency Multiply Register Bits 0 and Bits 1.
18.2
PWM Speed Control Registers
There are four PWM Speed Control registers: PWM0, PWM1, PWM2, and PWM3. These registers are
located in the LPC47N350 Mailbox Registers Interface. PWM0 is MBX92, PWM1 is MBX93, PWM2 is
MBX95, and PWM3 is MBX98 (see Table 17.1 on page 191).
The PWM Speed Control registers are in the LPC47N350 as shown in Table 18.3, Table 18.4 and
Table 18.5.
The default values for all the PWM speed control registers are 0x00. These defaults take effect on
VCC1 POR for PWM0, PWM1, and PWM3, and on VCC2 POR for PWM2 speed control register.
SMSC LPC47N350
201
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
