Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
System-to-8051
8051-to-System
INT1
SMI
32 8-bit
8051
HOST CPU
Mail-Box
Registers
Figure 17.1 System-to-8051 Mailbox Interface Registers Block Diagram
17.5.1 Mailbox Register 0: System-to-8051
If enabled, an INT1 will be generated when the System writes to Mailbox Register 0 (Table 17.4). The
interrupt source bit will be cleared when the 8051 reads this register.
After reading Mailbox Register 0, the 8051 can clear the register to “00H” by a dummy write to inform
the host that the register contents have been read.
Table 17.4 Mailbox Register 0 (System-To-8051)
0x82
0x7F08
VCC1
0x00
MAILBOX INDEX
8051 ADDRESS
POWER
DEFAULT
BIT
D7
D6
RC
D5
RC
D4
RC
D3
RC
D2
RC
D1
RC
D0
RC
MBX TYPE
(Note 17.4)
RC
R/W
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
8051 R/W
BIT NAME
Note 17.4 RC = Read-only register is cleared when written.
17.5.2 Mailbox Register 1: 8051-to-System
If enabled, an SMI will be generated when the 8051 writes to Mailbox Register 1 (Table 17.5). The SMI
interrupt will be cleared when the host reads this register.
Revision 1.1 (01-14-03)
194
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
