Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 17.2 Mailbox Registers Interface Configuration Controls (LDN9) (continued)
VCC1 &
HARD
SOFT
VCC2
VCC0
POR
INDEX
TYPE
RESET RESET POR
DESCRIPTION
RESERVED
MBX Primary Base Address High Byte
“0” “0” “0” A11 A10 A9
MBX Primary Base Address Low Byte
A6 A5 A4 A3 A2 A1
Activate
0x60
0x61
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
-
-
“0”
A7
A8
“0”
17.3
Mailbox Registers Interface Access Ports
The Mailbox registers access ports are runtime registers that occupy two addresses in the Host I/O
space (Table 17.3).
To access a Mailbox register once the Mailbox Registers Interface Base Address has been initialized,
write the Mailbox register index address to the MBX Index port and read or write the Mailbox register
data from the MBX data port.
Table 17.3 Mailbox Registers Interface Access Ports
ACCESS PORT
POWER
PLANE
VCC2
POR
VCC1
POR
NAME
HOST ADDRESS
HOST TYPE
MBX INDEX
MBX DATA
MBX Base Address
R/W
VCC2
0x00
-
-
-
MBX Base Address + 1
17.4
17.5
Mailbox Registers
There are 32 Mailbox Registers in the LPC47N350. The MBXA0–AF and MBX84– 91 Mailbox Registers
are general purpose registers. There are no interrupts for these registers.
The System/8051 Interface Registers
Mailbox Register 0, System-to-8051, and Mailbox Register 1, 8051-to-System, are specifically designed
to pass commands between the host and the 8051 (Figure 17.1). If enabled, these registers can
generate interrupts.
Mailbox Register 0 and Mailbox Register 1 are not dual-ported, so the System BIOS and Keyboard BIOS
must be designed to properly share these registers. When the host performs a write of the System-to-
8051 mailbox register, an 8051 INT1 will be generated and seen by the 8051 if unmasked. When the
8051 writes to the System-to-8051 mailbox register, the data is blocked but the write forces the register
to 0x00, providing a simple means for the 8051 to inform the host that an operation has been completed.
When the 8051 writes the 8051-to-System mailbox register, an SMI may be generated and seen by the
host if unmasked. When the Host CPU writes to the 8051-to-System mailbox register, the data is
blocked but the write forces the 8051-to-System register to clear to zero, providing a simple means for
the host to inform that 8051 that an operation has been completed.
PROGRAMMER’S NOTE: The protocol used to pass commands back and forth through the Mailbox Registers
Interface is left to the system designer. SMSC can provide an application example of
working code in which the host uses the Mailbox registers to gain access to all of the
8051 registers.
SMSC LPC47N350
193
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
