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47N350 参数 Datasheet PDF下载

47N350图片预览
型号: 47N350
PDF下载: 下载PDF文件 查看货源
内容描述: LEGACY免费的键盘嵌入式控制器, SPI和LPC接口对接 [LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 346 页 / 4406 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号47N350的Datasheet PDF文件第213页浏览型号47N350的Datasheet PDF文件第214页浏览型号47N350的Datasheet PDF文件第215页浏览型号47N350的Datasheet PDF文件第216页浏览型号47N350的Datasheet PDF文件第218页浏览型号47N350的Datasheet PDF文件第219页浏览型号47N350的Datasheet PDF文件第220页浏览型号47N350的Datasheet PDF文件第221页  
Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface  
Chapter 18 Pulse Width Modulators  
18.1  
Overview  
The LPC47N350 has four independent programmable Pulse-Width Modulators (PWM0, PWM1 and  
PWM2) that can be used for controlling fan speed. The PWM0, PWM1, and PWM3 have 6-bit pulse-  
width resolution, have the ability to force the PWM output always high or low, and they can generate  
several fan speeds (F  
) as shown in Table 18.1. The PWM2 however, generates fewer fan speeds  
OUT  
because there is no PWM2 STDBY CLOCK implementation, see Table 18.2.  
PWM0, PWM1, and PWM3 can be driven by the system clock when VCC2 is active, or by the  
32.768kHz standby clock (RTC) that is available when either VCC2 or VCC1 are active. PWM2 can  
only be driven by system clock when VCC2 is active. The PWM2 pin will tri-state when VCC2 = 0v (See  
Note 2.2).  
PROGRAMMER’S NOTE: The availability of the 32kHz standby clock is subject to the affects of the RTC clock  
control bits.  
The PWM Speed Control and PWM Control registers are accessible to both the Host and the 8051  
through the Mailbox register interface (see Chapter 17, Mailbox Register Interface).  
Table 18.1 PWM0, PWM1, and PWM3 Speed Control Summary  
FREQUENCY MULTIPLIER BITS  
(Note 18.7)  
PWMX  
CLOCK  
MULTI-  
PLIER  
BIT  
00 (1X)  
01 (2X)  
10 (4X)  
11 (8X)  
PWMX  
STDBY  
CLOCK  
BIT  
PWMX  
CLOCK  
CONTR  
OL BIT  
PWMX  
CLOCK  
SELEC  
T 1 BIT  
PWMX  
CLOCK  
SELEC  
T 0 BIT  
FOUT  
FOUT  
FOUT  
FOUT  
6-BIT  
DUTY  
(KHZ)  
(KHZ)  
(KHZ)  
(KHZ)  
CYCLE  
CONTR  
OL(DCC)  
DUTY  
CYCLE  
(%)  
Note 18  
.5  
Note 18.  
1
Note 18.  
2
Note 18.  
3
Note 18.  
4
Note 18  
.6  
Note 18  
.6  
Note 18  
.6  
Note 18  
.6  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
X
0 (low)  
15.625  
23.44  
0 (low)  
31.25  
46.875  
0.0814  
0.122  
62.5  
0 (low)  
62.5  
0 (low)  
125  
0
(DCC  
÷ 64)  
× 100  
1-63  
93.75  
0.1628  
0.244  
125  
187.5  
0.326  
0.488  
250  
0.407  
0.061  
31.25  
46.875  
0.0814  
0.122  
93.75  
0.244  
187.5  
0.488  
375  
0.977  
0
0
0
0
-
-
-
(high)  
(high)  
(high)  
(high)  
1
0
X
X
0 (low)  
0 (low)  
0 (low)  
0 (low)  
0
SMSC LPC47N350  
199  
Revision 1.1 (01-14-03)  
DATASHEET  
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