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47N350 参数 Datasheet PDF下载

47N350图片预览
型号: 47N350
PDF下载: 下载PDF文件 查看货源
内容描述: LEGACY免费的键盘嵌入式控制器, SPI和LPC接口对接 [LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 346 页 / 4406 K
品牌: SMSC [ SMSC CORPORATION ]
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Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface  
1. When the transmitter bit time (time between falling edges) exceeds 300us.  
2. When the transmitter start bit is not received within 25ms from signaling a transmit start event.  
3. If the time from the 1st (start) bit to the 10th (parity) bit exceeds 2ms.  
RD_DATA  
Read DATA bit: Reading this bit returns the current level of the PS2 channel’s Serial DATA pin. This  
bit is used for receiving bit-banged data over the PS2 channel. Bit-banging of the PS2 channel is  
enabled when the PS2_EN bit is set to 0. To receive data properly using this bit, PS2_EN must be set  
to 0 and the WR_DATA bit in the PS2 Channel’s Control Register must be set to 1.  
RD_CLK  
Read CLK bit: Reading this bit returns the current level of the PS2 channel’s Serial CLK pin. This bit  
is used when receiving bit-banged data over the PS2 channel. Bit-banging of the PS2 channel is  
enabled when the PS2_EN bit is set to 0. To receive bit banged data properly, the PS2_EN must be  
set to 0 and the WR_CLK bit in the PS2 Channel’s Control Register must be set to 1.  
Note 14.24 When PS2_EN = 0, high to low transitions on the CLK pin will generate a PS2 Chan  
interrupt. A timeout event or writing this bit low will not cause an interrupt.  
Note 14.25 When PS2_EN=1, bit-banging is disabled for any of the following 3 conditions:  
Time-out is active.  
300us following a time-out (Hold Time).  
RDATA_RDY = 1.  
14.3.5 SMSC PS/2 Status_2 Registers  
Table 14.8 SMSC PS/2_Status_2 Register  
-
HOST ADDRESS  
8051 ADDRESS  
POWER  
0x7F48  
VCC2  
0x00  
DEFAULT  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
-
-
-
-
-
-
-
-
HOST TYPE  
8051 TYPE  
R/WC  
R
R/WC  
R
R/WC  
R
R/WC  
R
XMIT_ST RX_BUSY XMIT_ST RX_BUSY XMIT_ST RX_BUSY XMIT_ST RX_BUSY  
BIT NAME  
ART_TIM  
EOUT_D  
D
ART_TIM  
EOUT_C  
C
ART_TIM  
EOUT_B  
B
ART_TIM  
EOUT_A  
A
PROGRAMMER’S NOTE: Always check that an SMSC PS/2 channel is idle, i.e. the RX_BUSY bit is ”0”, before  
attempting to transmit on that channel. Receive data may or may not be lost by setting  
an SMSC PS/2 channel to transmit while the RX_BUSY bit is asserted depending where  
in the message frame the transmit mode change occurs.  
RX_BUSY  
SMSC LPC47N350  
163  
Revision 1.1 (01-14-03)  
DATASHEET