Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
= 10: Receiver ignores the level of the Stop bit (11th bit is not interpreted as a stop bit).
= 11: Reserved.
WR_DATA
Write DATA bit: When PS2_EN=1, writes to the WR_DATA bit are accepted but result in no action other
than setting or clearing this bit. When PS2_EN=0, setting this bit to a 1 or 0 either floats or drives low
the PS/2 channel’s Serial DATA pin. This bit is used for transmitting bit-banged data over the PS2
channel. Bit-banging of the PS/2 channel is enabled when PS2_EN= 0.
Note: While the Hold timeout is in effect (300us following a Receive or Transmit Timeout) writes to this
bit are blocked.
WR_CLK
Write CLK bit: When PS2_EN=1, writes to the WR_CLK bit are accepted but result in no action other
than setting or clearing this bit. When PS2_EN=0, setting this bit to a 1 or 0 either floats or drives low
the PS/2 channel’s Serial CLK pin. Bit-banging of the PS/2 channel is enabled when the PS2_EN bit
is set to 0.
Note 14.17 While the Hold timeout is in effect (300us following a Receive or Transmit Timeout) writes
to this bit are blocked.
Note 14.18 When PS2_EN = 0, high to low transitions on the CLK pin caused by the peripheral will
generate a PS2 Chan interrupt. A timeout event or writing this bit low will not cause an
interrupt.
The default for the WR_DATA bit D6 in the four SMSC PS/2 Control Registers is “1”. The default in
earlier devices is “0” (Table 14.6). The VCC2 Power-on Default for each Control Register is 40h.
14.3.4 SMSC PS/2 Status Registers
Table 14.7 SMSC PS/2 Status Registers (A - D)
N/A
HOST ADDRESS
8051 ADDRESS
0x7F43
(CHAN A),
0x7F47
(CHAN B),
0x7F4B
(CHAN C),
0x7F4F
(CHAN D)
VCC2
0x00
POWER
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
R
R
R
R
R
R
R
R
RD_CLK RD_DATA
XMIT_
XMIT_IDLE
FE
PE
REC_
RDAT
_RDY
BIT NAME
TIMEOUT
TIMEOUT
SMSC LPC47N350
161
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
