Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Default = 0x40 on VCC2 POR only.
Note 14.19 There are four PS/2 Status Registers, one for each channel.
Note 14.20 XMIT_TIMEOUT, FE, PE, REC_TIMEOUT are cleared to zero upon a read of this register.
RDATA_RDY
Receive Data Ready: Under normal operating conditions, this bit is set following the falling edge of the
11th clock given successful reception of a data byte from the PS/2 peripheral (i.e., no parity, framing, or
receive timeout errors) and indicates that the received data byte is available to be read from the Receive
Register. This bit may also be set in the event that the PS2_EN bit is cleared following the 10th CLK
edge (see the PS2_EN bit description for further details). Reading the Receive Register clears this bit.
Note 14.21 An Interrupt is generated on the low to high transition of the RDATA_RDY bit.
REC_TIMEOUT
Under PS2 automatic operation, PS2_EN=1, this bit is set on one of 4 receive error conditions, and in
addition, the channel’s CLK line is automatically pulled low and held for a period of 300us (and until the
PS/2 Status register is read) following assertion of the REC_TIMEOUT bit:
1. When the receiver bit time (time between falling edges) exceeds 300us.
2. If the time from the 1st (start) bit to the 10th (parity) bit exceeds 2ms.
3. On a receive parity error along with the parity error (PE) bit.
4. On a receive framing error due to an incorrect STOP bit along with the framing error (FE) bit.
The REC_TIMEOUT bit is cleared when the Status Register is read.
Note 14.22 An Interrupt is generated on the low to high transition of the REC_TIMEOUT bit.
PE
Parity Error: When receiving data, the parity bit is clocked in on the falling edge of the 10th CLK edge.
If the channel has been set to expect either even or odd parity and the 10th bit is contrary to the
expected parity, then the PE and REC_TIMEOUT bits are set following the falling edge of the 10th CLK
edge and an Interrupt is generated.
FE
Framing Error: When receiving data, the stop bit is clocked in on the falling edge of the 11th CLK edge.
If the channel has been set to expect either a high or low stop bit and the 11th bit is contrary to the
expected stop polarity, then the FE and REC_TIMEOUT bits are set following the falling edge of the
11th CLK edge and an Interrupt is generated.
XMIT_IDLE
Transmitter Idle: When low, the XMIT_IDLE bit is a status bit indicating that the PS2 channel is actively
transmitting data to the PS2 peripheral device. Writing to the Transmit Register when the channel is
ready to transmit will cause the XMIT_IDLE bit to deassert and remain deasserted until one of the
following conditions occur:
1. The falling edge of the 11th CLK; upon a Transmit Timeout condition (XMIT_TIMEOUT goes high);
2. Upon the PS2_T/R bit being written to 0;
3. Upon the PS2_EN bit being written to 0.
Note 14.23 An interrupt is generated on the low to high transition of XMIT_IDLE.
XMIT_TIMEOUT
This bit is set on one of 3 transmit conditions, and in addition the channel’s CLK line is automatically
pulled low and held for a period of 300us (and until the PS/2 Status register is read) following assertion
of the XMIT_TIMEOUT bit during which time the PS2_T/R is also held low:
Revision 1.1 (01-14-03)
162
SMSC LPC47N350
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