Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Thv
IFREN
XAD R
XE
Trcv
Tadh
YADR
YE
Tads
Tprog
Tpgh
DIN
Tnv h
PROG
NVSTR
Tpgs
Tnv s
Figure 8.5 Flash Core Program Timing Diagram
Table 8.10 Flash Core Program Timing Values
NAME
MIN
MAX
UNITS
COMMENT
Tnvs
Tnvh
Tpgs
Tpgh
Tprog
Tads
Tadh
Trcv
5
µs
PROG/ERASE to NVSTR set up time
NVSTR hold time
5
10
20
20
NVSTR to program set up time
program hold time
40
25
program time
ns
address/data set up time
address/data hold time
recovery time
1
µs
Thv
ms
cumulative HV period
8.3.7.4
Page Erase Mode
In Page Erase mode, the CSI host interface uses the transparent address latch to maintain the page
address argument from the second host bus write cycle. The CSI flash interface then cycles the
appropriate controls to erase the page (Figure 8.6). The Flash Memory Array signals YE, SE, OE, MAS1
are always ‘0’ for Page Erase cycles; the XE signal behaves as shown in Figure 8.6. The CSI status
register BUSY bit is asserted as described in Section 8.3.6.1, "Busy Bit – D7," on page 94. At the end
of a Page Erase operation, the host interface and the flash interface idle until the next command is
given.
Revision 1.1 (01-14-03)
SMSC LPC47N350
DATA9S8HEET
SMSC [ SMSC CORPORATION ]
